Logic circuit

ABSTRACT

A monostable multivibrator circuit for producing a pulse of a fixed duration including a first D-type flip-flop having set, reset, clock and delay inputs, and a second D-type flip-flop having set, reset, clock and delay inputs. A trigger pulse triggers a change in state of the first D-type flip-flop, in turn causing a change in state in the second D-type flip-flop. The output of the second D-type flip-flop contains a capacitor storage circuit which serves to bypass the change in state of the second D-type flip-flop for a predetermined delay time, and feedback an exponentially increasing level to the first D-type flip-flop. When the charge across the capacitor reaches the threshold level of the first D-type flip-flop, the first flipflop output again changes condition, causing the second output to change correspondingly.

United States Patent 72] inventor Joseph A. Howells 3,497,725 2/1970Lorditch, Jr 307/273 21 A l N g g xg Primary Examiner-Donald D. Forrer E55 p 28 1969 Assistant Examiner-L. N. Anagnos 45 Patented 0a. 12, 1971Ammey Frank [73] Assignee Science Accessories Corporation Southport,Conn.

ABSTRACT: A monostable multivibrator circuit for produc- [54] LOGICCIRCUIT ing a pulse of a fixed duration including a first D-typeflip-flop 4 Claims 4 Drawing Figs. having set, reset, clock and delayinputs, and a second D-type flip-flop having set, reset, clock and delayinputs. A trigger US. pulse triggers a change in tate of the flip-flopin 307/215, 307/273, 307/276, 307/293, 328/ turn causing a change instate in the second D-type flip-flop. [51] Int. Cl H03k 3/10, The outputf the second D type fli f| contains a capacitor 3/12, 17/30 storagecircuit which serves to bypass the change in state of [50] Field ofSearch 307/273, th second D-type fli -flo for a predetermined delaytime,

272, 293, 269, 291; 328/207, 74, 7 and feedback an exponentiallyincreasing level to the first D- type flip-flop. When the charge acrossthe capacitor reaches [56] References Cited the threshold level of thefirst D-type flip-flop, the first flip- UNITED STATES PATENTS flopoutput again changes condition, causing the second out- 3,200,340 8/1965Dunne 307/269 put to change correspondingly.

5 B l STABLE 2 UNIT c. BISTABLE T S U N IT Q PATENTEDBET 12 ml 3,613.017

c BISTABLE Fig. I Y Q2 L C 86 THRESHOLD X 2 GROUND MIVENTOR. JOSEPH A.HOWELLS AGENT LOGIC CIRCUIT This invention relates to a monostable pulsegenerator, and more particularly to a monostable pulse generatoremploying logic elements.

The use of integrated circuits for monostable multivibrators presentadvantages in economy and ease of assembly. However, when comparativelylong pulse lengths are required from a monostable circuit, for example,up to microseconds and milliseconds in duration, difficulty isencountered. The reasons for such difficulty arise due to time constantswhich are lengthy and shallow, allowing the voltage input to anintegrated circuit gate to approach the transition region of switchinglevel too slowly and thereby cause multiple pulsing at the output.

'It is therefore the principal object of the present invention toprovide an integrated circuit arrangement which can be employed as amonostable multivibrator offering pulse lengths longer than heretoforeobtainable.

It is the secondary object to the present invention to provide amonostable multivibrator offering pulse lengths longer than heretoforeobtainable with a minimum of external components.

In accordance with the foregoing objects, the present invention employsfirst and second bistable circuits each having a first input forswitching the state of the bistable circuit in response to a shift inlevel in excess of the threshold level on the input in a firstdirection, and a second input for switching the state of the bistablecircuit in response to a shift level on the second input in a seconddirection. Application of a trigger pulse in the second direction to thesecond input of the first bistable circuit results in the output of thefirst bistable circuit responding thereto by shifting its output levelin the first direction. This first bistable circuit output is applied tothe first and second input of the second bistable circuit, and theoutput of the second bistable circuit responds to the first directionlevel shift on the first bistable circuit output for shifting the levelon the output of the second bistable circuit in the first direction. Thesecond bistable circuit has coupled to the output thereof a storagedevice responsive to the shift in level on the output of the secondbistable circuit for producing a level thereacross which increases overa time period in the first direction. This increasing level is coupledback to the first input of the first bistable circuit and, when thethreshold level of this feedback signal is exceeded by the increase inthe level of the feedback signal, the output of the first bistablecircuit undergoes a shift in level in the second direction. Since thesecond direction is now applied to the first and second input of thesecond bistable circuit, the second bistable circuit undergoes a changein output condition back to its initial level. Each of these bistablecircuits can be D-type flip-flop, each having a clock input, set input,reset input and a delay input. The delay and reset inputs of eachcircuit are clamped, and the first and second inputs are the clock andset inputs respectively. The storage means may include a capacitor aloneor in combination with a resistor series connected between a point ofpotential and a reference point, with the second bistable circuit outputbeing connected with the junction of the resistor and capacitor.

The foregoing objects and brief description of the present inventionwill be more apparent with reference to the following more detaileddescription and the appended drawings wherein:

FIG. 1 is a general block diagram of the inventive concept herein,

FIG. 2 is a graphical relationship of the waveforms at various points ofFIG. 1,

FIG. 3 is a more detailed illustration of the logic circuitry involvedin each of the bistable circuit units described in FIG. 1, and

FIG. 4, a detail ofFlG. 3.

Referring now to FIG. 1 there is shown a first bistable unit 10, asecond bistable unit 12, each of these bistable units having inputs 8,,and C,, and S,, and C,, respectively. Each of the bistable units and 12have outputs designated 0 and Q with an appropriate reference number,the output 0 being the complement of the output Q in each case. As shownin the FIG. 1, the output Q, of the bistable circuit is coupled to theinputs S, and C, of the bistable unit 12. Further, the output 6, of thebistable unit 12 is coupled to the input C, of the bistable unit 10. Acapacitor 14 is connected between outputQ, of the bistable unit 12 and areference point illustrated as ground.

To properly' understand the invention, it is important to note thebistable units 10 and 12 have certain defined characteristics ofoperation. More particularly, the bistable unit 10 and 12 will undergo achange in state only when a signal level on the inputs to the S, and S,terminals of either unit undergoes a transition from a high level to alow level, or as may more conventionally be described, from a one to azero. The reverse is true, however, with respect to the C inputs. Thatis, the C input is operative to switch the bistable unit only when theinput level thereon shifts from a low level to a high level. Thus, theoperation of the units 10 and 12 as illustrated in FIG. 1 can beefficiently described with reference to the waveform diagrams of FIG. 2.As shown in FIG. 2 the condition of the bistable units 10 and 12 aresuch that during the initial period t, the output Q, of the bistableunit 10 is assumed to be in its low condition, whereas the output Q, isassumed to be in the high position. The complimentary output of thebistable unit 12, 6,, is therefore in the low condition. Toward the endof the time period t,, the signal level on the input line S, is driventoward the low condition by a suitable external source T as for exampleconventional logic circuitry and representing a trigger pulse. As aresult of this, the output Q, undergoes a level change from the lowcondition to the high condition. Since the output Q, is coupled to theinput C, of the bistable unit 12, a similar change in the output Q, alsotakes place. The corresponding complementary change in the output Q,also takes place, resulting in the signal level proceeding in adirection from low to high at the output 6,. The presence of thecapacitor at the output of Q, will shunt the leading edge of thewaveform produced by Q, to the indicated ground point such that thesignal level at the input C, at the end of the period t, will proceedfrom the high level to the low level and during the perioclt r, willundergo a rise to a threshold point. This threshold point is the pointat which the signal level appearing on C, becomes sufficient to causethe bistable unit 10 to undergo a change in state. The time periodnecessary to achieve threshold is selectable in a well known andconventional manner employing the exponential characteristic of acapacitor. However, the capacitor is only indicative of the many knowntypes of storage devices usable for time delay. When the thresholdpoint, indicated in FIG. 2 as X, is achieved, the output level Q,returns from the high level to the low level. Since the output of Q, iscoupled to the input S, of the bistable unit 12, the shift from a highlevel to a low level on S, changes the condition of the bistable unit 12and the bistable unit 12 will achieve its initial condition. This isindicated during the time period t, FIG. 2. Since the arrangement inFIG. I utilizes separate gating switching inputs for efiecting thechange of state of the bistable units 10 and 12, an accurate time delayperiod over a relatively long region can be achieved without cause forconcern of transitions appearing due to the shallow rise of the timedelay circuit with respect to the threshold in which the associatedflip-flop switches.

Referring now to FIG. 3, a more detailed arrangement of the circuit ofFIG. 1 is presented. Each of the gates indicated therein are NAND gates,of conventional design. Corresponding legend numerals have been used inFIG. 3 to indicate correspondence with FIG. 1. Thus, each of thebistable units 10 and 12 are constructed of six NAND gates, arranged asshown, to produce the functions as stated in connection with FIG. 1. Theoperation of a NAND gate is illustrated in the logic tables of FIG. 4.The logic circuit performs the function of an AND gate with an invertingfunction, so that the output appearing at C is the inverted product ofthe input supply to A and B, as indicated in the logic table in FIG. 4.

For the purposes of increasing the angle with which the capacitor chargeapproaches the threshold value of the input C, of the bistable unit 10,a resistance 16 is connected between the capacitor 14 and a source ofpotential Vcc which, as indicated in FIG. 2, is in excess of thethreshold value, and

represents the value to which the capacitor level will charge beforebeing clamped to the threshold level at the input C,. An additionalresistance 18, which may be variable, is added for the purposes oftrimming the value of 16 and for adjusting the values of the timeconstants and the resultant pulse width.

The units 10 and 12 are each conventionally available and bothobtainable together in a single structural environment, such as forexample the SN7474N Integrated Circuit, a dual type D fiip-fiop,manufactured by Texas Instruments.

When utilizing the foregoing integrated circuit, the following pulsewidths were obtained with the various stated values of R and C. Thechart below is intended as exemplary only.

u |l IF Kn u rF l.5 UF 1 US 30 US 40 US 20 1 US 450 US 550 US I 0.2 MS2.8 MS 3.5 MS

200 0.5 M 5.5 MS 6.5 MS

300 0.7 MS 8.0 MS 9.0 MS

400 0.9 MS 9.0 MS MS 500 L1 MS 9.8 MS 16 MS As illustrated in FIG. 3,the reset terminals R and R although each may be operative to producechange in states of the bistable units 10 and 12, are not in factutilized but rather are connected to a fixed reference point having ahigh-level value. The D inputs to each of the units 10 and 12, althoughalso operable to change in condition of the bistable units, aresimilarly connected to a fixed reference point having a lowlevel value.

Since certain modifications and changes or alterations may be made inthe above disclosed embodiment without departing from the scope of theinvention here involved, it is intended that all matter contained in theabove description and shown in the accompanying drawings shall beinterpreted in an illustrative and not in a limited sense.

lclaim:

l. A monostable pulse generator comprising first and second bistablecircuits each having a first input for switching the state of saidbistable circuit in response to a shift in level in excess of athreshold level on said first input in a first direction, and a secondinput for switching the state of said bistable circuit in response to ashift in level on said second input in a second direction, means forapplying a trigger pulse in said second direction to the second input ofsaid first bistable circuit, the output of said first bistable circuitresponding to said trigger pulse for shifting the level thereon in saidfirst direction, means applying said first bistable circuit output tosaid first and second input of said second bistable circuit, said secondbistable circuit responsive to said first direction level shift of saidfirst bistable circuit output for shifting the level of the output ofsaid second bistable circuit in said first direction, capacitive storagemeans coupled to said second bistable circuit output and responsive tosaid shift in level thereon for producing an output level increasingexponentially over a time period in said first direction, and meanscoupling said storage means output level to the first input of saidfirst bistable circuit, said first bistable circuit output undergoing ashift in level in said second direction as said level applied to saidfirst input of said first bistable circuit exceeds said threshold levelof said first bistable circuit, said second bistable circuit responsiveto said latter shift in level through said second input thereof forrestoring said second bistable circuit to its initial condition.

2. The combination of claim 1 wherein each of said bistable circuits areD-type flip-flops, each said first input being a clock input, each saidsecond input being a set input, and each further including a delay inputand a reset input, means connecting both said delay inputs to a firstreference point, and means connecting both said reset inputs to a secondreference point.

3. The combination of claim 1 wherein said storage means comprises acapacitor and resistor series connected between a point of potential anda reference point, and said second bistable circuit output is connectedto the junction of said resistor and capacitor.

4. The combination of claim 2 wherein said storage means comprises acapacitor and resistor series connected between a point of potential andsaid reference point, and said second bistable circuit output isconnected to the junction of said resistor and capacitor.

1. A monostable pulse generator comprising first and second bistablecircuits each having a first input for switching the state of saidbistable circuit in response to a shift in level in excess of athreshold level on said first input in a first direction, and a secondinput for switching the state of said bistable circuit in response to ashift in level on said second input in a second direction, means forapplying a trigger pulse in said second direction to the second input ofsaid first bistable circuit, the output of said first bistable circuitresponding to said trigger pulse for shifting the level thereon in saidfirst direction, means applying said first bistable circuit output tosaid first and second input of said second bistable circuit, said secondbistable circuit responsive to said first direction level shift of saidfirst bistable circuit output for shifting the level of the output ofsaid second bistable circuit in said first direction, capacitive storagemeans coupled to said second bistable circuit output and responsive tosaid shift in level thereon for producing an output level increasingexponentially over a time period in said first direction, and meanscoupling said storage means output level to the first input of saidfirst bistable circuit, said first bistable circuit output undergoing ashift in level in said second direction as said level applied to saidfirst input of said first bistable circuit exceeds said threshold levelof said first bistable circuit, said second bistable circuit responsiveto said latter shift in level through said second input thereof forrestoring said second bistable circuit to its initial condition.
 2. Thecombination of claim 1 wherein each of said bistable circuits are D-typeflip-flops, each said first input being a clock input, each said secondinput being a set input, and each further including a delay input and areset input, means connecting both said delay inputs to a firstreference point, and means connecting both said reset inputs to a secondreference point.
 3. The combination of claim 1 wherein said storagemeans comprises a capacitor and resistor series connected between apoint of potential and a reference point, and said second bistablecircuit output is connected to the junction of said resistor andcapacitor.
 4. The combination of claim 2 wherein said storage meanscomprises a capacitor and resistor series connected between a point ofpotential and said reference point, and said second bistable circuitoutput is connected to the junction of said resistor and capacitor.